Synthesis of data transmission circuits starting from behavioral HW descriptions

Data transmission rates are rising steadily, accompanied by the requirements to shorten the design cycle for faster and more complex VLSI chips containing data transmission and protocol control logic. One procedure to shorten the design cycle is to describe the behavior of a system in a HW description language like VHDL and perform high level synthesis thereafter. We describe a FSM generator (FSM-G) which avoids the usage of a HLS tool and translates the VHDL specifications of data transmission circuits into a behavioral RT VHDL description. The behavioral routing table (RT) description can be further synthesized by an RT- and logic synthesis tool. The results of applying the FSM-G to ATM switch controller modules are shown at the end of this paper.