Design of a wideband transmit delta-sigma DAC

In this paper a wideband CDMA single-carrier transmitter IF digital-to-analog converter (DAC) based on delta-sigma (/spl Delta//spl Sigma/) modulation is presented. The /spl Delta//spl Sigma/ modulator is a 5-bit 12th order bandpass-type with a sampling frequency of 16 times the chip rate. The implementation consists of FIR interpolation filters, a /spl Delta//spl Sigma/ modulator, a binary weighted D/A converter and an analog postfilter. This paper discusses mainly the digital /spl Delta//spl Sigma/ architecture, and its performance on adjacent channel power ratio (ACPR) and error vector magnitude (EVM). Concerning on the given specifications, also linearity errors due to element mismatch distortion in the D/A conversion are discussed. The modulator is implemented in Xilinx. Virtex 400 series FPGA family.