Comparative study of low-voltage performance of standard-cell flip-flops

The static single-phase D flip-flop is the basic memory element in the standard cell based design methodology for digital integrated circuits. In low-power high-speed performance designs, pipelining in conjunction with voltage scaling has proven to be an efficient approach to achieve the targeted low-power performance. The efficiency of the flip-flop at low power supply voltages will therefore play an increasingly important role. In this paper, a comparison of the efficiency of six different D flip-flops operating at different voltages are presented and discussed. All circuits in this paper have been designed in a 0.6 /spl mu/m CMOS technology and the results have been obtained from analog simulation. This study shows that power savings are possible in power-driven synthesis by including different flip-flops that are based on different design styles in the standard cell library.