A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system

The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. In this paper, we present a high throughput 8/spl times/8 2D DCT/IDCT architecture which is well suited for the application in real time image or video system. Instead of the transport RAM in the traditional architecture, an overlapped row-column operation is used that can reduce the total latency of the pipelined structure. The multiplication is accomplished by using look-up tables and a partial sum adder to reduce the area and cycle time. It possesses no matrix transposition and is suitable for VLSI implementation. We have designed a DCT/IDCT chip using this architecture via the Compass standard cell library under the TSMC 0.35 /spl mu/m 1P4M process. The chip occupies 4278.4 /spl mu/m/spl times/4278.4 /spl mu/m and consists of 119,181 transistors. The simulation results show that a clock rate of up to 100 MHz can be achieved.