Two-dimensional array layout for NMOS 4-phase dynamic logic

A novel layout approach of array cell (AC) architecture is described, which is dedicated to nMOS 4-phase dynamic logic. An AC is constructed of (M/spl times/N)+2 nMOSFETs which constitute each type of nMOS 4-phase logic gates. A graph theoretic approach to the nMOSFET placement in conjunction with a simulated annealing procedure is exploited for the area reduction in the layout design of the AC. A number of experimental results demonstrate the practicability of the proposed approach.