18 to 37.5GHz Linear and Efficient 5G Power Amplifier with Adaptive Biasing Technique

An efficient linear power amplifier (PA) which uses a new adaptive bias circuit is implemented in TSMC 28-nm bulk CMOS process targeting 5G wireless communication systems. An optimized PA core is presented using FET stacking with the intermediate node matching technique, and RLC feedback. The adaptive bias circuit improves the PA efficiency and cancels the PA nonlinearity by controlling the PA quiescent current ramping across the PA input power. The fabricated single stage PA shows a measured gain of 10 dB, 3-dB bandwidth (BW) from 18 to 37.5 GHz (70%), and 16.8 dBm of maximum output power (Psat) with peak PAE of 41%. The proposed PA achieves a measured EVM/ACPR of −26.25dB/−29.2dBc at 10.12 dBm Pout with a 14.1% PAE using a 400MHz 64QAM 5G NR signal at 24GHz.