Design of Efficient Scan Flip-Flop

Design For Testability (DFT) is a technique used while designing the Integrated Circuit (IC) to add features to the hardware design which helps in testing the design. Scan insertion is one of the DFT techniques which is used in sequential circuits. It is most popularly used as the testability of the circuit will be much better and the design can be easily tested. Scan insertion involves the insertion of scan flip-flop consisting of a D flip-flop with an extra multiplexer and additional scan input and scan output pins. The addition of extra circuitry increases the area, delay and power consumption which is undesirable. Hence, there is increase in the amount of silicon used and in the test time, which leads to lower profits. In this paper, two novel and efficient Scan flip-flop designs have been implemented consuming less power, area and delay. The two unique Scan flip-flop designs namely Gate Diffusion Input based D flip-flop and modified Transmission Gate based Scan flip-flop have been developed in Cadence Virtuoso. An improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively. A decrease of 47% and 56.73% was observed in peak-power consumption in functional and test modes respectively.