Design of Low-Power DDR Controller and DRAM for Deep Learning and Server Applications

This paper focuses on the design of low power dynamic random access memory (DRAM) for deep learning and server applications by implementing i) a modified memory cell array, ii) partial refresh mechanism with controller command modification for half access and, iii) machine learning algorithm to identify the type of data to be stored in DRAM while using a hybrid memory system. The proposed design techniques help in reducing power consumption in a memory hungry system. Simulation results in Cadence Virtuoso Design Environment shows a 49.9% reduction in total power dissipation during a read operation, 38.4% power reduction during all bank refresh operation and 22.3% power reduction during per bank refresh operation. Logistic regression classifier has been used to predict the type of memory suitable for storing data based on data type, number of 0s and 1s, frequency as the training set with a training accuracy of 90.8% and prediction probability of 0.867.