Modified Nine Level Multi Level Inverter Topology for Trinary Sequences with Reduced Switches and Switching Losses

This paper presents a newly modified nine level multilevel inverter (MLI) topology. This MLI uses reverse voltage circuit concept and the input dc sources employs trinary asymmetric sequence. It provides highest output voltage level with minimum dc supply and electrical switch count in comparison to alternative sequences. Utilizing of trinary sequence MLI generates all additive and subtractive combinations of input dc voltages at the output. This topology is implemented on 9-level asymmetric MLI using less number of active and passive elements. Unipolar pulse width modulation technique is employed to generate gating pulses. The proposed topology is simulated in MATLAB/Simulink and efficiency, THD, power losses are determined. Results indicate better performance, i.e., lesser losses, minimal switches, and cost with acceptable THD.