Cross-Layer Digital Design Flow for Space Applications

Reliability and fault tolerance needs in space applications pose additional requirements to the chip design flow. In order to successfully cope with space related issues, cross-layer measures need to be taken at different levels of design abstraction. In the first place, Single Event Effects (SEEs) need to be well understood and modelled at gate and circuit level. Such evaluation needs to be considered in the process of corresponding rad-hard library design. At cell/gate and RTL levels different methods of redundancy can be applied to accommodate the increased reliability requirements. Since redundancy approaches are very expensive in terms of area, power and performance overhead, effort needs to be spent in optimization. Such optimization could be accomplished through the selective hardening of the most sensitive gates. For example, at gate level the most sensitive combinational cells can be hardened, while at R TL level only critical registers are made fault tolerant. Finally, the design flow could address the highest (system) level of complex digital systems. In this case resilient mechanisms could be implemented, enabling the use of system level redundancy in an adaptive, self-aware and optimal way. In this paper we will propose a rad-hard design flow which supports the evaluation of fault tolerance methods at different abstraction layers.