A Low-Complexity Shifting-Based Conflict-Free Memory-Addressing Architecture for Higher-Radix FFT

Conflict-free addressing (CFA) techniques are necessary for Fast Fourier Transform (FFT) hardware. For low radices, well-proven XOR-based addressing architectures are available in the literature. Applications such as wireless communication use higher FFT radices, more processing elements, and a larger number of memory sets for a continuous flow of data. In the existing CFA techniques, the complexity increases with increasing radices or memory sets. In the proposed technique, the higher number of memory sets and radix are leveraged to advantage. A novel scheme is suggested to reduce the complexity using a progressive shifting technique. The mathematical basis of the scheme is derived here and illustrated with an example of 512-point radix-16 FFT. The proposed and existing CFA architectures are designed using Verilog and implemented in the Semiconductor Laboratory, Chandigarh, 180 nm SCL library. The synthesis results show that the proposed scheme achieves a 33% area reduction, 23% lower power consumption, and 39% improvement in execution time performance compared with the existing XOR based schemes. The area reduction factor further improves with a higher number of FFT points.