Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits

In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper bounded across multiple cut points in the same cycle. The use of an Asynchronous STA (ASTA) engine, which does not cut cycles, and properly bounds slews across cycles is a possible solution, which can indeed serve as an upper bound over SPICE transistor level similations. We contrast STA and ASTA-based gate-level simulations with transistor level SPICE simulations to demonstrate the impact of timing errors for 12 asynchronous control circuits, implemented by the Petrify tool, in a 0.25μm technology library. We show that STA-based simulation results are incorrectly more optimistic than ASTA, and it is possible for the simulation period to even be faster than SPICE, which is a major timing error.