On-Die Clock Tree Low PSIJ Through PDN Optimization

On-Die Power Distribution Network (PDN) optimization for achieving low Power Supply Induced Jitter (PSIJ) on clock tree is put forth. A chip having a distribution of differently sized decoupling capacitors coupled to a distributed power supply conductor grid, where the sizing of the decoupling capacitors is selected based on the spatial locality of the noise contributed by individual clock buffers of a clock distribution network, to achieve controlled low PSIJ.