Higher Aspect Ratio TSV Structure ECP Bottom-Up Plating Process

With the rapid development of the electronic industry, the demand on mini-size, low power consumption and high reliability becomes inevitable to electronic products. Based on Moore's law decreasing the feature size of the integrated circuits is approaching a bottleneck. Recently wafer-level vertical miniaturization 3D Through-Silicon-Via (TSV) package integration becomes an alternative solution to breakthrough the bottleneck of Moore's law down scaling in design, process and cost. Correspondingly, due to copper's higher conductivity, less resistant to electromigration, copper is widely used material to fill the TSV via. Conventionally the copper metal layer deposition and planarization process contains several process steps: PVD, ECP, annealing, and CMP. Electrochemical plating (ECP) is a key process for copper via filling, which is required to achieving void-free and seam-free via filling, and with a minimized the copper overburden thickness. In wafer level mass production, the thinner overburden is beneficial to reduce wafer stress and shorten process time and reduce process cost. The ECP process's performance is dependent on seed layer pre-treatment, chemistry, chemistry mass transfer, and plating current etc [1]. In this study, the 300mm wafer is pre-treated in a pre-wet chamber by DIW; after that the wafer will be located in a horizontal plating chuck and face down immerged in the plating chemistry with protecting voltage and current; the plating chamber will control the flow rate distribution, plating current, distance between anode and plating rotation speed. These parameters dominated via filling, overburden thickness and within wafer plating uniformity.