Performance analysis of different Tunnel Field Effect Transistors (TFET) device structures with their Challenges

Tunnel Field Effect Transistor (TFET) is emerging as a suitable device to operate at a very low power. TFET overcomes the challenges faced by MOSFET based on its different switching mechanisms of band to band tunneling (BTBT) which makes it unique in terms of very low power consumption. TFET facilities steeper slope(<60mV/decade), improved ON/OFF current ratio and low on current and very low leakage current. In this paper, various device structures of TFETs and different parameter variations such as junction width, tunneling barrier width, thickness of gate dielectric and silicon on Insulator (SOI) thickness have been studied. TFET structures had been modified over time and more advanced technology been added to increase its on-current, improve its ambipolarity and overall to obtain steeper slope. The investigation is centered on different technological methods to improve performance.