Implementation and Comparison of Direct mapped and 4-way Set Associative mapped Cache Controller in VHDL

This paper presents the implementation of design of a non-pipelined processor that generates memory read/write requests to a direct-mapped and a 4 - way set associative mapped cache controller frequently and examines their performances by calculating Cache hits versus misses. The paper also briefly explains cache memory, the Least Recently Used (LRU) algorithm, cache controller, memory mapping techniques. Following that, a cache controller based on Finite State Machine has been implemented for direct-mapped as well as Four-way set-associative synchronous Cache (buffer) memory of 256 bytes whose size of the block is 128 bits or 16 bytes (by default). A multi-banked interleaved main memory system comprising of 4memory banks of 1K byte each has been designed and used. The implementation is done using VHDL, and the simulation has been performed using Eda playground, an online simulation tool. The maximum clock frequency is 110 MHz.