Power Consumption and Delay Comparison of a Modified TCFF with Existing FF Implemented using FinFET and Load Test Circuit Analysis

In this paper a single phase clock flip-flop has been introduced. This is a modified version of topologically compressed flip-flop. It consist of 19 transistors which is two transistor less than the Topologically Compressed Flip-Flop (TCFF) and a cross coupled PMOS transistor use in the slave latch which is taken from the master of a static contention free single phase clock flip-flop. The power and delay analysis has been performed of the modified TCFF. It is also compared with the other flip-flop circuits in terms of power and clock to output delay. All the circuit has been implemented on the 18 nm finFET technology. This circuit is simulated at different capacitive load from 0.01 fF to 10 fF. The maximum power saved by 38.01% and minimum power saved by 6.83%.