Performance Analysis of Full Adder Circuit using Conventional and Hybrid Techniques

Adders are widely used in many digital circuits and play an integral role in the implementation of various logic circuits. From the starting days, efforts are being made to design the circuit with fewer numbers of transistors. In VLSI design speed, area and power always have trade-offs. The conventional full adder requires 32 transistors (32T) to implement. This circuit gives superior performance in terms of speed but consumes a lot of area and power. Efforts are being made by various means to decrease the number of transistors to design the same logic which will help to achieve a similar or better speed with lesser power and area consumption. We analyzed and compared the full adder circuit using 28T, 20T, 18T, 14T, and 10T. The analysis is done on Cadence Virtuoso at 45nm, 90nm, and 180nm technology nodes using generic process design kit (gpdk) CMOS cell libraries. The comparison is done based on three key parameters that are speed, area, and power consumed by the circuit. The process corner analysis and post-layout simulation are performed on 45nm technology for three circuits which are good at one key parameter between power, delay, and area.