Scaled Back End of Line Interconnects at Cryogenic Temperatures

At scaled nodes, Back End of Line (BEOL) interconnect resistance increases super-linearly and creates performance and energy bottlenecks. While it is known that metal resistance deceases with temperature, understanding and quantifying the behavior of interconnects from a foundry process design kit (PDK) at low temperature is critical for designing circuits and systems operating at cryogenic temperatures including Quantum and Superconducting Computers and other High-Performance Systems. In this letter we use parametric path based ring oscillators along with reference ring oscillators and Metal-on-Metal Capacitors for 22nm Fully Depleted Silicon on Insulator to measure RC delays of BEOL elements from room temperature to 4.2K. The extracted resistance of the elements show reduction of up to 30% for M1/M2, 33% for M3-M6 and 19% for Via1. With simple assumptions for interconnect structure, we perform least-squares fit of Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models with line-Edge roughness incorporated in the model using the Namba Model. The empirically fitted parameters track well with literature. The fitted model is within 3.7% error of all experimental results.