Field Programmable Gate Arrays Implementation of Two-Point Non-Uniformity Correction and Bad Pixel Replacement Algorithms

In this paper, the hardware architecture for two-point non-uniformity correction (TPNUC) and bad pixel replacement (BPR) algorithms are presented based on field-programmable gate arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture modeled using C++ in the High-Level Synthesis (HLS) tool is presented. The design is tested on an FPGA fabricated at a 16 nm technology node. The design achieves a maximum frequency of 300 MHz and one pixel per clock. A thermal camera development platform (FullScale USB3A) with a resolution of 640×480 is used as the source for the raw video. The simulation results from MATLAB and FPGA posed close similarities.