RTL Implementation of MCMC-based Constraints Solver

Functional hardware verification is one of the most challenging areas in the hardware design cycle. With the increase in the complexity and size of the design, the time needed for verification becomes the largest part of the total design time. The most recent technique in practical verification is constrained random simulation. This method needs a solver to produce random input stimuli that satisfies a pre-defined set of input constraints. The efficiency of the overall verification process depends critically on the speed of the constraints solver and the distribution of the generated solutions. In this paper, we propose hardware acceleration for RTL constraints solver integrated with SystemVerilog. The solver is based on Markov Chains Monte Carlo methods.