A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s

PCI Express^® (PCIe^®) specification has been doubling the data rate every generation in a backward compatible manner every two to three years, while maintaining the same latency, power, channel reach, cost, and reliability profile. It also provides architected support for alternate protocols such as those with coherency or memory semantics to run on PCIe PHY, in addition to the PCIe protocol. As a result, protocols such as Compute Express Link® (CXL®) as well as several CPU-CPU proprietary cache coherency links such as Ultra-Path Interconnect (UPI) run on PCIe PHY due to its low-latency and power-efficiency characteristics. PCIe 6.0 specification is adopting PAM-4 signaling to deliver 64.0 GT/s per Lane. A Flit-based approach with a light weight Forward Error Correction, strong CRC, and a low-latency link retry mechanism is used to meet the stringent low-latency, high bandwidth efficiency, scalability, and high reliability goals of PCIe applications. In this paper, we propose enhancements to the above mechanisms to have 0 latency impact while maintaining the bandwidth efficiency and high reliability for alternate protocols involving coherency and memory semantics where any latency adder may have an adverse impact on performance, while using the same PCIe 6.0 PHY. Our results demonstrate that these goals are achievable with PCIe 6.0 PHY while meeting the latency, bandwidth, reliability goals with multiple protocol support.