Impact of process variants on SEU tolerance of CMOS/SOS circuits

Summary form only given. The impact of several process variants on single-event-upset (SEU) tolerance of the RCA/GE 6167/RZ, 16 K CMOS/SOS SRAM was determined. The RAMs were fabricated with a 3- mu m gate process. In epitaxial films consisting of three crystal structures and two p impurity profiles. The devices were evaluated in the SEU test facility at Brookhaven Laboratory. Although some test cells showed improvements in total dose hardness, there was no degradation in SEU tolerance. The SEU tolerance of a CMOS and CMOS/SOS error detection and correction circuit was also evaluated. The circuits were gate arrays processed with a 1.2- mu m gate process. The circuit could not be upset up to a cross section of 149 MeV-cm/sup 2//mg. The CMOS circuit has an error rate approximately 4E-7/day. The SEU test data are summarized in a table.<>