Dynamic Response and Filtering Capability Improvement of $\alpha \beta$-Frame Cascaded Delayed Signal Cancellation Based PLL

Blocking the grid voltage imbalance through the $\alpha \beta$-frame delayed signal cancellation ($\alpha \beta$DSC) operator requires a relatively high delay value of $1/4$ cycle. Since the dynamic behavior of the $\alpha \beta$-frame cascaded delayed signal cancellation based phase-locked loop ($\alpha \beta$CDSC-PLL) depends on the total delay length of the cascaded operators, this value can slow down the dynamic response. In this paper, however, inspired by the delayed signal cancelation (DSC) concept, an enhanced $\alpha \beta$-frame DSC operator, which removes the grid voltage imbalance with a delay length of only $1/12$ cycle, is proposed. The small-signal model of the suggested frequency adaptive operator is derived, making the tuning procedure and stability analysis easy yet effective. Due to the shorter delay length, using the proposed operator in the $\alpha \beta$CDSC-PLL structure leads to a higher speed-of-response and, therefore, a less phase-angle error during grid voltage scenarios. Moreover, when the total delay length decreases, the filtering capability will be improved using more operators at the chain of the cascaded DSC operators. The performance of the $\alpha \beta$CDSC-PLL and its suggested enhanced structure, benefiting from the proposed operator, are compared through theoretical analysis and experimental tests, which verify that the proposed structure offers a better dynamic response and filtering capability.