Highly Stacked GeSi Nanosheets and Nanowires by Low-Temperature Epitaxy and Wet Etching

The eight stacked Ge_0.75Si_0.25 nanosheets, the seven stacked Ge_0.95Si_0.05 nanowires, and the six stacked Ge_0.95Si_0.05 nanowires without parasitic channels are demonstrated. These highly stacked channels are made from 18 epilayers consisting of a Ge buffer, nine heavily P-doped Ge sacrificial layers, and eight GeSi channel layers with the low growth temperature (350 °C and 375 °C) to ensure the entire epilayers metastable without dislocations in the channels. The isotropic wet etching by H₂O₂ and NH₄OH + H₂O₂ is used for the channel release and the removal of the parasitic channels, respectively. The delicate interplay between epilayer design and wet etching is implemented to fabricate the highly stacked GeSi channels. High inter-channel uniformity of the eight stacked Ge_0.75Si_0.25 nanosheets is obtained due to the superior etching selectivity. High ${I}_{\mathrm{\scriptscriptstyle ON}}$ per stack and per footprint of the seven stacked Ge_0.95Si_0.05 nanowires and the six stacked Ge_0.95Si_0.05 nanowires without parasitic channels are achieved due to the high mobility ${L}_{4}$ valleys and nanowire conduction. The reduced subthreshold slope (SS) and improved ${I}_{\mathrm{\scriptscriptstyle ON}} / {I}_{\mathrm{\scriptscriptstyle OFF}}$ are obtained by parasitic channel removal. The record ${I}_{\mathrm{\scriptscriptstyle ON}}$ of $120~\boldsymbol \mu \text{A}$ per stack ( $4600~\boldsymbol \mu \text{A} / \boldsymbol \mu \text{m}$ per channel footprint) at ${V}_{\mathrm{\scriptscriptstyle OV}} = {V}_{\mathrm{\scriptscriptstyle DS}} = 0.5$ V is reached among reported Ge/GeSi 3-D nFETs.