Test Bench Optimization for Better Simulation Performance

Verification time is a major factor in determining the time to market of the product. In order to save time, reusable test benches are developed and are modified as and when the design undergoes changes. As new features are added in RTL, new configurations and functions are added in the test bench to enable verification of the new features. The test bench is nothing but a source code in itself. The coding style determines the amount of resources that will be used during simulation. Poorly coded logic results in increased consumption of memory and time leading to degraded simulation performance. Since a number of engineers work on a piece of code, it is essential to write readable and easily understandable code. Therefore, it is essential to keep in mind the best coding practices, readability and maintainability of the code while developing the test bench. This work proposes to enhance the coding style and improve the readability and maintainability of the test bench used to verify the L2 cache which is part of a larger design. Profiling and certain switches provided by the simulator were used to identify the performance issues pertaining to simulation. Assertions with large memory footprint were identified and the memory usage decreased by 8.675% after the changes. The address randomization logic was optimized post which the CPS improved by 26.38%. The code for preloading the cache was enhanced to improve the readability and maintainability.