Bit Error Rate Performance of Hybrid Interleaver in Turbo Codes

An Interleaver is a component or a system tool that is useful for saving processing time by rearranging the input bitstreams. The approach to design a hybrid interleaver is to cascade different interleavers such as the 3rd generation partnership project interleaver and block interleaver et cetera. As the number of bits increasing, the memory and time required for coding and decoding increases due to which some applications completely avoid using interleavers to save time resulting in high Bit error rates. This paper proposes a method to design a cascaded, two-stage, hybrid interleaver and also analyzes its bit error rate performance. The hybrid interleaver reduces coding and decoding times of turbo codes and maintains good bit error rate levels that are achieved in other interleavers such as the 3rd generation partnership project interleaver and block interleaver.