An Analytical Model for Circuit Reliability Estimation

With the continuous scaling of CMOS technology and growing density of circuit chips, accurate and efficient calculation of reliability for integrated circuits is becoming a critical issue. One of major obstacles in calculating the reliability efficiently with high accuracy is the difficulty in dealing with reliability correlations among signals. This paper proposes an analytical model to estimate the correlations using structural and probabilistic information within a local area of circuits, as well as to propagate the correlations throughout the circuit in a topological order of logic gates, which makes the computation time linear to circuit size. Simulations show that the resulting percentage errors in estimating output reliabilities are less than 2%.