Abstract:
This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver op...Show MoreMetadata
Abstract:
This work presents simulation results of a CMOS 1.2-V single-ended source-series-terminated (SST) voltage-mode electrical link driver in a 65 nm technology. The driver operates in two driving modes. The first mode uses symmetric pre-emphasis feedforward equalization to drive a short electrical link which introduces a total loss of 16 dB including electro-static discharge (ESD) and wire bonding losses at 10 GHz. The second mode drives a VCSEL diode through an electrical link exploiting asymmetric equalization. Through simulation, this dual-mode proposed driver operates up to 20 Gb/s and is estimated to dissipate 40 mW of power.
Date of Conference: 09-11 August 2021
Date Added to IEEE Xplore: 13 September 2021
ISBN Information: