Optimizing Encoder and Decoder Blocks for a Power-Efficient Radix-4 Modified Booth Multiplier

The conventional modified Booth multiplier comprises an encoder and a decoder, which produce partial products by adjusting the multiplicand according to 3-bit windows generated in the segmentation of the multiplier. The partial products are added later with the necessary left shifts in each one. They produce accurate results, more useful in processes where the error is not acceptable, like divisions, transformations and filters. This paper proposes optimizing the radix-4 Modified Booth encoder (MBE) and decoder (MBD) for a power-efficient multiplier. Two new topologies are presented for optimizing the encoder and decoder set so that the partial product terms avoid unnecessary operations. The proposed encoder and decoder structures are highly regular, with few logic gates, and easily parallelized for any number of input bits. The results show that the proposed optimizations reveal gains in area and power compared to the conventional multiplexer-based multiplier. When applying the proposed multiplier in the butterflies of the Fast Fourier Transform, the proposed multipliers are more efficient with gains in the area, power, and power-delay-product (PDP) compared with the multipliers using the ‘*’ operator from the literature.