A pipelined digital frequency synthesizer based on feedback

In this paper, a fast, compact, and all-digital synthesizer capable of generating sine and cosine waveforms simultaneously is presented. The sinusoidal signal generation in the synthesizer is based on complex multiplication and feedback. A novel pipelined hardware architecture is presented. In addition to the general pipelining algorithm, simulation and synthesis results for a 16-bit signal synthesizer using a 0.35 /spl mu/m 3.3 V 4-metal n-well standard cell CMOS-process are presented. The simulated maximum clock frequency of the 3-level pipelined synthesizer is 160 MHz. The estimated worst case spurious free dynamic range (SFDR) is 78 dBc.