CMOS VLSI implementation of 16-bit logarithm and anti-logarithm converters

This paper presents two unique 16-bit binary-to-binary logarithm and binary logarithm-to-binary converters including their CMOS VLSI implementations. Both converters are implemented using combinational logic only, and they calculate Mitchell's logarithm and anti-logarithm approximations in a single clock cycle. Simulations of the 0.6 /spl mu/ CMOS design for the logarithm and anti-logarithm converters ran at 150 and 178 MHz, respectively. A novel leading one detector circuit is designed to obtain the leading one position.