Design and prototyping of a /spl Sigma//spl Delta/ decimator filter for DECT standard

Deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and an FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.