Supervised Machine-Learning Approach for the Optimal Arrangement of Active Hotspots in 3-D Integrated Circuits

3-D integration is now considered a new paradigm for the semiconductor packaging industry to sustain Moore’s law. Vertical stacking of semiconductor chips provides high power density in a given footprint area. However, owing to increased integration, 3-D ICs having multiple core areas (hotspots) on each stack layer can often be prone to thermal interaction between the stack layers (Interlayer) and within the stack layers (Intralayer). In this work, three layers with three core hotspot areas on each layer are considered. This article proposes an optimization methodology to optimally arrange the hotspot active core areas in three layers of 3-D IC. The optimization methodology aims to minimize the maximum core temperatures and maximize the temperature uniformity in the stack. The optimal placement of hotspot core areas in each layer not only aids in reducing the thermal interaction but also aids in improving the temperature uniformity by thermal spreading. A sampling algorithm based on Latin Hypercube Sampling that incorporates the “nonoverlap” constraint is demonstrated in this study. A Genetic algorithm coupled with supervised machine-learning-based artificial neural network is employed as an optimization methodology. The article introduces a unique arrangement parameter for the multiple numbers of hotspots in various layers that could well represent the problem under consideration. The methods and results from this article could be efficiently used to perform a thermal aware core hotspot arrangement of multilayer multihotspot 3-D integrated circuits for any operating conditions.