Design of Digital Architecture for Custom Implementation of Cordic Algorithm

An efficient way of obtaining trigonometric, hyperbolic, linear, and logarithmic is provided by the CORDIC algorithm. In this algorithm bit shifting operation replaces multiplication and iterative addition will result in accurate values of such trigonometric functions. Not only it is saving the area but also improves the throughput. This algorithm has become a widely researched area in the field of vector rotated DSP applications. This paper explores the basic CORDIC algorithm and implements it on FPGA using VHDL coding. Uniqueness in the proposed CORDIC algorithm is that 4-bit input will cover all the values of angle in four quadrants having a resolution of 22.5°. Using recent technology, we can have to utilize more hardware in order to achieve speed constraints. A serial iterative CORDIC uses less hardware with more latency so, here to have high throughput parallel iterative hardware is used. But The bit-parallel variable shift shifters require high fan-in. As FPGA provides both flexibility as well as speed it is much better choice for implementing CORDIC algorithm. The proposed CORDIC algorithm is simulated on Vivado 2019.2 and implemented on the Xilinx Spartan 3E board. The simulation results which are shown below verify the authenticity and validity of the designed CORDIC algorithm.