High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures

In this letter, a low-power 1-bit full-adder (FA) cell is proposed based on the transmission gate (TG) to attain a special module for generating full-swing Carry output. The cell benefits from the high driving capability for both Sum and Carry outputs when embedding in multistage structures like ripple-carry adders (RCAs), compressors, and multipliers. The proposed TG-based FA has a total die area of 60.02 $\mu \text{m}^{2}$ , while the average power, delay, and power-delay-product (PDP) are 10.829 $\mu \text{W}$ , 3.1954 ns, and 34.603 fJ, respectively. The results introduce the FA cell as an efficient gate for integrated circuits (ICs).