A verification method for power-off protection mechanism of embedded chip non-volatile memory

This paper proposes a verification method of power-off protection mechanism for non-volatile memory, which is suitable for the application scenarios where the data needs to be protected when power-off occurs when the non-volatile memory is erased or written. This method can verify the correctness of the power-off protection mechanism, i.e. whether the data operated after the power-off event can maintain atomicity. This verification method gives the specific verification method, but does not limit the specific details of the implementation.