Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition

Signed digit (SD) addition is applied to the design of a new floating-point (FLP) multiplication-add fused (MAF) unit. This adoption, together with the proposed two-step normalization method, can reduce the three-word-length addition that is required in the conventional FLP MAF unit to two-word-length addition. Furthermore, sign reversion of the intermediate mantissa that requires three-word-length carry propagation in the conventional MAF unit is replaced by only single-word sign detection. These two improvements can enhance the speed and cost of the MAF unit significantly. With the use of the SD addition, the circuit of the unit can be designed in a more regular and simple manner, which is a property that is desired in VLSI design. The proposed FLP MAF unit has been designed and simulated by using Verilog hardware description language. The functions of the designed unit are verified to be correct.