Low-power multipliers by minimizing inter-data switching activities

By using the radix-4 Booth algorithm, low-power 2's complement multipliers are developed by minimizing inter-data switching activities. Before performing multiplication, one of two input data with a smaller dynamic range is partitioned into Booth codes, thereby increasing probabilities of partial products being zero. In addition, functional blocks for adding zero preserve their previous input states. As compared to the conventional Wallace-tree multiplier, the two 16/spl times/16-bit multipliers proposed herein are demonstrated to have lower power dissipation.