FPGA-based Geometric Test Pattern Generator

This paper shares a technique to generate a simple VGA test screen using VHDL and Verilog for used in an FPGA chip. Test pattern is a display that when correctly displayed, one can quickly acknowledge that the whole system is working well. Usually the pattern is designed to check fullness of display, aspect ratio, correctness of synchronizations, frequency response, resolution, and - in case of polychromatic monitor - the color. In this paper the construction is made for monochromatic and color display using only simple geometry. One usually use this technique when developing a display module from the scratch using FPGA and the bitmap-reading module (or ASCII ROM module) is yet to be built. In such cases, a quick functionality test is very useful. The technique was successfully implemented using VHDL and Verilog in a standard development board. We hope students of electrical and computer engineering program can confidently start from this test pattern for the design of their next project.