Error Tolerant MBIST Design with Efficient High Throughput and Low Power Reversible Techniques

In order to minimize ATE (Automatic Test Equipment) time and expense, deep submicron systems contain a large number of memories that demand lower area and quick access time, so an automated test strategy for such designs is needed. When it is upgraded, the memory arrangement becomes complicated. Due to higher rate of memory size incorporation, the device's production expense is declining, and the cost of testing is rising. Memory BIST (Built-in Self-test) is a promising response to this predicament, incorporating test and fix circuitry to the memory itself and offering a reasonable yield. A novel SRAM cell is suggested in this concept and the cell with Fredkin and Feynman gates was planned. For parameter optimizations, the GDI-based reversible gate architecture is implemented. This upgrade requires improved memory construction at the most powerful high throughput and low latency-based density. The updated Low Transition Linear Feedback Shift Register (LFSR) dependent clock splitting technique is built to produce addresses for this SRAM to reach both rows and columns. In addition to implementing the principle of BIST and Decimal Matrix codes, error detection including correction is also incorporated to eliminate each small memory cell for enhanced memory design.