A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes

We developed a unified physical and statistical compact model of Bias Temperature Instability (BTI) effects on scaling technology nodes towards robust VLSI design, with an excessive amount of complex stress/recovery pattern characterization, ultralong-term aging prediction, and technology of statistical variability (TSV) analysis, realizing cycle-to-cycle/device-to-device reliability evaluations. This model is based on a 2/4-state Defect-Centric (DC) theory and verified by TCAD simulation, providing a deep insight into the properties of the defects (e.g., energy level distribution, occupancy probability etc.). By calibration to Fin-FET experiments (of down to 14 nm node), it is successfully implemented into BSIM-CMG for analysis of dynamic time evolutionary and dynamic voltage scaling. This physics-, variablity-, and tolerance-aware model has the potential to boost the design technology co-optimization (DTCO) flow of reliability in VLSI to the next generation of technology nodes.