Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

We report on forksheet N- and PFETs co-integrated with gate-all-around nanosheet FETs. The forksheet short-channel control is on par with nanosheets down to 22nm gate length (SSSAT=66-68mV/dec). Forksheet ION and IOFF characteristics are improved by post-channel-release wet clean optimization, attributed to gate stack interface trap density reduction. Dual work function metal gates are integrated at 17nm N-P space, highlighting a key benefit of forksheets for CMOS area scaling.