Programmable Delay-Line with High-Resolution Time Steps Implemented in a Digital-to-Time Converter IP-Core for FPGAs and SoCs

In this paper, we present an innovative Digital-to-Time Converter Programmable Delay Line (DTC-PDL) IP-Core to generate a delay with a high resolution for Xilinx Field-Programmable Gate Array (FPGA) and System-on-Chip (SoC) devices. Compared to solutions already present, such as Application-Specific Integrated Circuits (ASICs), the strength of our IP-Core is the reduced hardware overhead and the high flexibility, which makes our proposal easily upgradeable and ready to be integrated in existing systems, without the need of a complete redesign. The system achieves excellent performance thanks to the use of specialized resources, yet abundant in modern FPGAs, reaching a resolution of the pulse generated in the order of tens of picoseconds. Our programmable delay line consists in a Time-to-Digital Converter (TDC) that measures the delay between an input pulse and the internal reference clock rising edge, programming a block that implements the Nutt Technique to generate a resolute signal. Using this interpolation technique, a high Full-Scale Range (FSR) is achieved while maintaining very high resolution and precision. Indeed, the use of high frequency digital counters allows to obtain the coarse part of a time wave, while the high resolution is guaranteed by the use of Xilinx primitives called IDELAYE2. In this way we are able to obtain a system with a FSR of 1.30 ms and a resolution in the order of tens of picoseconds, with a jitter below few tens of picoseconds rms. The DTC IP-Core works on all Xilinx 7-series FPGA and SoC platforms and it has been successfully validated on a Avnet Mini-Module Plus, which mounts an Xilinx Kintex-7 XC7K325T-1.