Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

The endurance of the HfO₂-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (T_ramp), which is the time to reach the PG/ER voltage, and the hold time (T_hold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10⁴ by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long T_ramp but short T_hold are desirable to suppress the interface trap generation in FeFET. The relation between T_ramp, T_hold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).