Criteria to reduce failures induced by EMI conducted on the power supply rails of CMOS operational amplifiers

In this work we study, from an electrical point of view, the behaviour of a CMOS operational amplifier when electromagnetic interference (EMI) are conveyed to the supply rails. In particular, with reference to the classical two-stage CMOS topology, we show that the amplifier undergoes strong failure when subjected to EMI conveyed to the positive supply, while it is only moderately sensitive to interference conveyed to the negative supply. Finally, through detailed circuit analyses and extensive circuit simulations, we demonstrate the electrical origin of such failure and suggest a compensation technique that allows a strong increase in IC reliability.