Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability

The IEEE 1687 Std. provides an efficient access methodology for embedded instruments in complex system-on-a-chip designs by introducing reconfigurable scan networks. This flexibility enables the reduction of the overall test access time, which significantly decreases the test costs compared to the conventional daisy-chaining method. However, the new access methodology strictly requires effective test schedulers that consider multi-power domains with individual constraints.This work proposes a novel test scheduler that orchestrates the Boolean Satisfiability problem in conjunction with Pseudo-Boolean optimization techniques. The effectiveness of the proposed scheduler is proven by considering networks with over one thousand of so-called instruments forming industrial representative benchmark candidates.