Cu Pillar Bump Design Parameters for Flip Chip Integration

Cu pillar has gradually become the flip chip package interconnect method of choice. Cup pillar bumping are not only the current work horse in the industry but also an enabler for fine pitch flip chip packages, system-in-package (SIP), 2.5D and 3D packages, and sophisticated heterogeneous integration. With the advanced Si nodes that uses ultra low-k dielectrics (ULK) materials, which are extremely sensitive to the higher stress levels induced by Cu pillar bumps in comparison to solder bumps, a proper choice of Cu pillar parameters becomes essential to achieving ULK's reliability. There have been many experimental and empirical data sets gathered so far for various Cu pillar bump designs, coupled with a large number of actual process and equipment limitations at various bumping houses. Combining that with individual die pad designs and different layouts, it is not easy to sift through and conclude which design rules to follow, and it is next to impossible to say that one set of design rules will apply to all packages being considered. On the other hand, wafer foundries usually send out a reference design guide that has been verified to be reliable as a result of their in-house limited chip packaging integration (CPI) studies. Unfortunately, such guides sometimes are treated by Si designers as inflexible rules to follow, resulting in a sacrifice of optimization to individual design needs. The same is true for outsource assembly and test (OSAT's) houses which oftentimes apply one bumping rule to fit all package strategies, which often results in reliability compromises of specific packages. In this paper, a theoretical study is performed through two models, simplified beam without shear and shallow beam with shear model. The goal is to provide a theoretical foundation and some guidelines to Cu pillar bump design parameters, such as under bump metallurgy (UBM) shape, size, pillar height, and their effects on stress level within the ULK layer. With these guidelines, each individual Cu pillar design could be optimized with greater success. To validate analytical solutions, we present finite element model results for one package using Cu pillar with a 12nm Si wafer node considering a number of possible design parameters. The finite element analysis results are in agreement with the analytical solutions and the package has successfully passed reliability test. The analytical solutions presented here can be used as reference guides to create more robust and efficiently designed Cu pillar flipchip packages