Effect of using High-k Dielectric Material on Transconductance of a Strained-Si PMOS

The performance of MOS devices degraded due to short channel effects like DIBL, velocity saturation, quantum confinement and hot carrier degradation. Due to scaling the mobility of the MOS devices reduces. To overcome the shortcomings several structures like silicon-on-insulator (SOI), strained si (SS) are evolving. In this paper, SS PMOS with high-k dielectric is designed on strained si/relaxed $Si_{0.82}Ge_{0.18}$ heterostructure using Silvaco TCAD Simulator. By the help of ATLAS 2D simulator, the electrical parameters are analyzed. Arora model is used to design the SS PMOS device. The proposed device is compared with SS PMOS device. An 80% enhancement of transconductance is achieved in SS PMOS with high-k dielectric device as compared to SS PMOS device at room temperature. The influence of SS PMOS with high-k dielectric device over SS PMOS device is shown both at low temperature and room temperature.