Analysis and Simulation of A Gate-Controlled DDSCR Embedded with MOS-Path for Adjustable Holding Voltage in HV ESD Protection

High-voltage power integrated circuits such as automotive electronics and power management have become a significant branch of semiconductor industry. Faced with harsh working environment, high-voltage power integrated circuits generally require robust electrostatic discharge (ESD) protection schemes. However, the deep snapback of traditional Silicon Controlled Rectifiers (SCR) gives rise to a low holding voltage, implying they cannot be directly applied for high-voltage ESD protection due to CMOS latch-up. Based on above issues, this paper proposes a Gate-Controlled DDSCR embedded with MOS-path (EMGC-DDSCR) for high and adjustable holding voltage. The electric field of polysilicon gates push ESD current into deeper discharging path inside the device, which reduces surface current and artificially lengthens the SCR path in longitudinal direction without consuming extra layout. Theoretically, holding voltage is increased while high failure level of the device is maintained. A typical numerical model of SCR holding voltage is constructed and analyzed. The channel conduction of EMGC-DDSCR is altered by changing cathode MOS gate bias, which affects positive feedback of the SCR structure. The adjustable holding voltage is thus achieved. Two SCR structures in this paper are designed based on 0.18μm standard BCD process design rules. Silvaco TCAD platform is utilized to perform two-dimensional DC scanning simulation and TLP transient simulation on both devices. Simulation results are well consistent with theoretical analysis, which provides a new idea for HV SCR design with a single structure suitable for multiple ESD windows.